Please use this identifier to cite or link to this item: http://hdl.handle.net/123456789/666
Title: Power Consumption Analysis for Different SRAM Cells
Authors: Sarah Mousa Alnuwaihedh 
Supervisor: Dr. Mahmoud Bennaser
Keywords: SRAM : Power Consumption
Issue Date: 2017
Publisher:  Kuwait university - college of graduate studies
Abstract: Static random access memory (SRAM) has become a crucial part of the VLSI (Very Large Scale Integration) field, and it is widely used because it has the ability to store vast amounts of data, processing it within a short timeframe. SRAM designs vary depending on the number of transistors. For example, the SRAM that contains six transistors is called 6T SRAM. The SRAM cells used in this study include conventional 6T, controlled 6T, single-ended 7T, double-ended 7T, and 9T types. As SRAM is one of the most used memory types of today’s technologies, which each have their own specifications, we conducted this study to help researchers and developers find the SRAM cell that best fulfills their aims and requirements. The goal of this thesis is to identify the required power and area for different SRAM cells via simulating and analyzing each type of SRAM separately. We calculated the dynamic and the leakage power for several SRAM types in three different temperatures (25°C, 50°C, 125°C). Also, area is calculated for all cell types in this study. In this study, 0.5-micrometer CMOS (Complementary Metal Oxide Semiconductor) technology was used. This study was conducted at Kuwait University in November 2015. The data for this thesis was collected by simulating cells using L-Edit for the cell layout and PSpice for simulation and for getting the values. The results show that each cell type had different dynamic and leakage power. As more transistors were added, the leakage power was reduced (i.e., the stack effect). Although the leakage power increased as the temperature increased, there was no impact on dynamic power as the temperature changed. We found that the 9T SRAM cell had the least leakage power and the biggest area (about 9.6X more than that of the 6T SRAM cell), while the leakage power of the conventional 6T SRAM cell was about 3X higher that of the 9T SRAM cell. The main contribution in this thesis is to do a complete study (simulation and analysis) for several SRAM cells. Future work can be directed toward minimizing the power in the cells that founded to have high power values.
URI: http://hdl.handle.net/123456789/666
Appears in Programs:0612 Computer Engineering

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